1. Field of the Invention
This invention relates to Read Only Memory (ROM) manufacturing techniques and more particularly to code implanting during ROM manufacturing.
2. Description of Related Art
ROM devices are standard components of modern computer systems. A ROM comprises an array of Metal Oxide Semiconductor Field Effect Transistors (MOSFET's) arranged in columns and rows, wherein predetermined MOSFET's are either permanently conductive or nonconductive as a function of the variety of transistor. The alternative on/off operation of these devices states of the MOSFET's is adapted to use for storage of data, which remains in the device when the external power supply is off.
A ROM device includes an array of parallel, closely spaced lines regions formed of a heavily doped impurity in a semiconductor substrate having an opposite type of background impurity. On the surface of the substrate an insulating layer is formed thereon. Another array of closely spaced conductive lines formed on the surface of the insulating layer is arranged at right angles to the spaced lines in the substrate. Insulating layers are formed on the upper array of conductive lines. A metallurgy layer connects the two arrays of lines to circuits to address the lines and to read the data stored in the RAM, as is well known in the art.
At the intersection of a conductive line in the upper array which is commonly referred to as a "word line" and a pair of adjacent lines in the substrate, known as the "bit lines", a MOSFET is formed. The spaced lines in the substrate comprise the source and drain for the MOSFET. The conductive word line serves as the gate electrode of the MOSFET. Certain predetermined MOSFET's can be made permanently conductive by forming a region of an impurity of the same type as that in the bit lines, between adjacent bit lines and beneath the corresponding conductive line. These permanently conductive regions are known as code implants, and they are placed in the substrate to provide specific binary data.
The conventional manufacturing process is to form the code implant regions very early in the ROM fabrication process, since an annealing step is required to activate the implanted impurity and also to recrystallize any implanted areas of the substrate. The annealing process involves heating the substrate above an acceptable temperature, which would damage the completed device, since the aluminum metallization, conventionally used, is damaged above a temperature of from about 400.degree. C. to about 450.degree. C. for more than a minimum time interval, and the maximum possible temperature is the melting point of aluminum which is about 660.degree. C.
FIGS. 1A and 1B are a flow chart of the prior art process for manufacturing a ROM. Function 10 comprises the early stage of the prior art process for forming a ROM commencing with an N- doped semiconductor substrate upon which a P-well is formed by doping with an opposite (P-) type of dopant. Above the P-well is formed a silicon dioxide gate oxide layer about 200 .ANG. thick. Above the gate oxide layer, word lines are formed from a layer of polysilicon followed by a layer of a refractory silicide (polycide), each about 1500 .ANG. thick. The refractory silicide is selected from silicides of refractory metals such as Ta, W, Ti and Mo.
In function 11, silicon dioxide spacers are formed adjacent to the word lines and the conventional N+ implant and P+ implant processes are performed.
After a long hiatus contrasted with the steps in FIG. 2, (described below) which shows the process flow chart of the instant invention, in function 12, the prior art process continues with application of a layer of photoresist which is then patterned with a mask and exposure of the resist.
In function 13, boron B.sup.11 dopant ions are implanted adjacent to the spacers with an ion implanter operating at an energy level of about 180 keV.
In function 14, the prior art process continues with formation of a layer 24 of USG (Undoped Silicon Glass) by APCVD (Atmospheric-Pressure Chemical Vapor Deposition) to a thickness of about 1,500 .ANG..
In function 15, a BPSG layer is deposited to a thickness of about 7,200 .ANG. with boron (B) about 3.0% and phosphorous (P) about 4.6%. The process used in the prior art to deposit the BPSG layer 26 also comprises APCVD.
In function 16, the prior art device of function 15 has been heated to reflow the BPSG layer at a temperature of about 900.degree. C. which reflows the BPSG layer 26, thereby planarizing the USG layer 24 and BPSG layer 26 with a combined thickness remaining at about 8700 .ANG..
In function 17, the device of function 16 is subjected to formation of contacts by photolithography.
In function 18, the device of function 17 is coated with a metal layer, followed by a process of photolithography and etching.
Next in function 19, a passivation step is performed.
In function 20, pad lithography and etching are performed.
In function 21, formation of the alloy is done.
In function 22, a wafer acceptance test involving yield prediction is performed.
Finally in function 23, a wafer level circuit test is performed about two weeks after function 12, which demonstrates the long time which elapses between the deposit of the implant when using the prior art process when contrasted with the one day which elapses between functions 12 and 23 when the present invention is employed as illustrated in FIG. 2 where similar functions have similar numbers.
The conventional mask ROM programming methods include: programming by field oxide, channel ion implant, etc. It is desirable for a mask ROM that small die size, coincides with short turn around time. However, it is difficult when a conventional process, such as one of the above mentioned methods, is used for the process to achieve a short turn around time. This invention uses existing facilities in an industrial laboratory to achieve the short turn around time goal in an industrial factory.
In Hong et al "Very Late Programming Process for Mask ROM" 08/125,182 filed Oct. 23, 1993 a process of ROM manufacture includes buried bit lines, covered by a thin gate oxide layer on which polysilicon word lines are formed which are covered with a thick film of BPSG between 3,000 .ANG. and 8,000 .ANG. thick. Metallization is applied formed of aluminum, a refractory metal, refractory metal silicide or heavily doped polysilicon. The refractory metal or the refractory metal silicide are stated to be preferred because they will withstand higher temperatures than aluminum and can be annealed at 850.degree. C. for about 15 minutes or 900.degree. C. for 5 minutes. A resist layer is applied and patterned to define a code implant pattern. The code implantation is performed preferably with boron B.sup.11 ions at a power of about 180 keV with an implantation dosage of about 1 E 13 to 1 E 14 atoms/cm.sup.2. After implantation of the ions they are activated. Preferably, a passivating layer of silicon dioxide or silicon nitride in the range of 5,000 .ANG. to 10,000 .ANG. thick deposited by PECVD. When the metallization is aluminum with a thick barrier metal layer, the activation of the implanted ions and recrystallization "must be done by rapid thermal annealing (RTA). In the critical RTA process . . . the device must be heated to a temperature not greater than about 650.degree. C., but above a temperature of 550.degree. C. and maintained for a time in the range between 3 and 10 minutes. The atmosphere of the RTA process may be an inert gas such as nitrogen."
Applicants find that it is difficult to employ an implant energy of 180 keV to implant through a thickness of 3,000 .ANG. or particularly through a structure comprising a 9,000 .ANG. thick combination of BPSG and a polycide word line. Accordingly an object Of this invention is to use a thinner layer of BPSG with a thickness less than about 3,000 .ANG..
The double charge method has a very low throughput, which is not well adapted to mass production.
The late programming etch back method is not adapted to a practical application from the point of end point issues and it is more complicated than desired. Accordingly an object of this invention is to avoid the late programming etch back method.
An object of this invention is to employ a lower temperature annealing process to achieve a high throughput.
Another object of this invention is an improved narrow metal pattern processing technique.
A further object of this invention is to employ an improved thinner BPSG layer.
This invention provides a method to achieve the shortest turn around time and pre-wafer out device accept prediction functions.
The turn around time is about one day from ROM lithography to the end of the fully finished wafer process.
An object of this invention is a lower temperature annealing process.
Another object of this invention is an improved narrow metal pattern processing technique.
A further object of this invention is to employ an improved BPSG layer in the process.
Advantages of this invention include the following:
1. After the whole process is completed (except for the process of custom code parts) then programmed by using a low cost production type (compared with high energy implanter) medium current implanter to achieve shortest turn around time. PA1 2. Medium current implant results low damage of Antana effect and low sidewall bleeding effect (smaller cell size can be applied.) PA1 3. Pre-wafer out device accept test can be performed during stage for custom code. Circuit test may be performed directly after process finished. PA1 4. Thin oxide passivation layer also can prevent metal corrosion problem during the stage period. PA1 a) forming a plurality of closely spaced line regions with a first impurity type in and adjacent to the surface of a semiconductor substrate having a background impurity of a second opposite type, PA1 b) forming a thin insulating layer of the surface of the substrate, PA1 c) forming a plurality of closely spaced, parallel, thin, electrically conductive lines on the thin insulating layer arranged orthogonally relative to the line regions, PA1 d) forming a thin glass insulating layer over the conductive lines, PA1 e) reflowing the glass insulating layer to provide planarization thereof, PA1 f) forming contacts, PA1 g) forming a metal layer on the glass insulating layer, PA1 h) depositing a resist layer on the metal layer, PA1 i) exposing the resist layer with a metal pattern, etching through the resist layer to form patterned metal and removing the resist layer, PA1 j) depositing a second resist layer onto the patterned metal, and exposing the second resist layer with a custom code pattern, PA1 k) developing the resist layer into a mask, PA1 l) etching exposed areas of the insulating layer to form openings exposing selected areas of the conductive lines, PA1 m) implanting impurity ions into the substrate adjacent to the conductive lines through the openings in the insulating layer, PA1 n) removing the resist layer, PA1 o) passivating the device with a thin layer, PA1 p) activating the implanted impurity ions by annealing the device at a temperature less than or equal to about 520.degree. C. in forming gas (comprising nitrogen gas, N.sub.2 and hydrogen gas, H.sub.2) or nitrogen gas, N.sub.2,